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IEEE Std 1800-2017

IEEE Std 1800-2017 是电气电子工程师学会的技术标准，题为“IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language”；公开目录标为已被替代（Superseded），著录年份为 2018 年。

Aggiornato · rev 1 · Altri nomi：1800-2017 1800-2017 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language

IEEE Std 1800-2017（IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language）是电气电子工程师学会的技术标准。公开目录将其标为已被替代（Superseded），著录年份为 2018 年，主题领域包括 Computing and Processing[1]。参见IEEE 标准。

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