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IEEE Std P1800/D6 · Versies

IEEE Std P1800/D6 是电气电子工程师学会的草案，题为“IEEE Unapproved IEEE Draft Standard for System Verilog: Unified Hardware Design, Specification and Verification Language (Superseded by P1800/D6)”；公开目录标为非现行（Inactive），著录年份为 2005 年。